Charge detecting circuit with variable capacitor and method for same

ABSTRACT

A method of detecting the charges which photo-electric conversion elements produce in correspondence to the density data of minute regions in an original image. In the method, a variable capacitor is charged with the capacitance set to a large value, and the voltage developed across the variable capacitor is detected with the capacitance set to a small value, whereby the voltage to be detected is increased as much, with an improvement in the signal detection accuracy.

BACKGROUND OF THE INVENTION

This invention relates to an image reading section in an image readingdevice which is employed as image reading means in facsimiles, imagescanners, etc., and more particularly to a charge detecting method ofdetecting the charges which photo-electric conversion elements producein correspondence to the density data of minute regions in an originalimage, and a charge detecting circuit for practicing the method.

An image reading device set in close contact with an original in orderto read the image of the latter comprises: a photo-electric conversionelement array made up of a plurality of photo-electric conversionelements arranged in a line; and a drive IC for driving thephoto-electric conversion element array. The drive IC includes switcheswhich are adapted to select the photo-electric conversion elementsforming the photo-electric conversion element array one after another toapply the charges generated in the photo-electric conversion elements toone output line in a time-sequential manner.

The photo-electric conversion element array has a light receivingsection made up of a plurality of photo-electric conversion elements.Each element is formed by arranging a metal electrode and a transparentconductive film on both sides of an amorphous silicon (a-Si) layer, soas to detect optical charges formed by light reflected from an originalimage.

A simple equivalent circuit for one bit of the image reading device isas shown in FIG. 7. The circuit operates as follows: When a light beamreflected from an original and including data on the density of a smallregion of the original image is applied to a photo-diode PD, an opticalcurrent Ip flows in the photo-diode PD to produce an optical chargetherein. The charge thus formed is stored in a capacitor Cp formed bythe light receiving element and a capacitor CL formed by wiring(hereinafter referred to as "a wiring capacitor CL", when applicable),so that the voltage Va of an input line of an amplifier A is increased.The amplifier A detects the voltage Va with high input impedance. Theoutput of the amplifier A is applied by means of an analog switch SW toan output line T_(out) for every bit, to form a time-series signal.Thereafter, the amplifier A is reset; more specifically, the input lineof the amplifier A is grounded through a reset switch RS. Therefore, asthe wiring capacitor CL decreases, the voltage Va of the input line ofthe amplifier A is increased, and accordingly the signal detectionaccuracy is increased.

The above-described image reading device is disadvantageous in that,since a number of photo-electric conversion elements 70 are drivenindividually, it is necessary to use a number of driving ICs with theresult that the manufacturing cost is increased as much. In order toovercome this difficulty, a matrix drive type image reading device hasbeen proposed in the art which is lower in manufacturing cost with thenumber of driving ICs decreased.

The matrix drive type image reading device, as shown in FIG. 8,comprises: K photo-electric conversion element groups each consisting ofn photo-electric conversion elements 70; and switching elements T_(ll)-T_(kn) which are provided for the photo-electric conversion elements70, respectively. The switching elements T_(ll) -T_(kn) are connected ton common signal lines 80. For every block, the switching elements T_(ll)-T_(kn) are turned on by gate pulses applied to gate lines Gl-Gk, sothat several bits are connected to the common signal lines at the sametime, thus being processed in a parallel mode.

For simplification in description, the operation of the image readingdevice will be described with reference only to the first block. It isassumed that, when the switching elements T_(ll) -T_(ln) are turned off,a light beam reflected from an original which includes data on a smallregion of the original image is applied to the image reading device. Inthis case, in response to the light beam, optical currents Ip flow, thusproducing optical charges. The charges thus produced are stored in thelight receiving element capacitors C_(Pll) -C_(Pln) and in the overlapcapacitors C_(GD) between the drains and gates of the switchingelements. When the switching elements T_(ll) -T_(ln) are turned on, theaforementioned charges are distributed to the overlap capacitors C_(GS)between the sources and gates of the switching elements, the wiringcapacitors C_(Ll) -C_(Ln), the light receiving element capacitorsC_(Pll) -C_(Pln), and the overlap capacitors C_(GD). Therefore, in orderto sufficiently transfer the charge to the wiring capacitors C_(L), thecapacitance must be much larger than the light receiving capacitanceC_(P), and the overlap capacitances C_(GS) and C_(GD). The changes inpotential of the common signal lines 80 due to the charges stored in thewiring capacitors C_(Ll) -C_(Ln) are transmitted through amplifiersA_(l) -A_(n) to an output line T_(out) by closing analog switches SW_(l)-SW_(n) in a driving IC 81 one after another, so that they are detectedin a time-sequential manner. The above-described operation is carriedout for every block, so that an image signal is formed for one line ofthe original.

In the image reading device described with reference to FIG. 7 whichemploys the potential detecting method, the signal detection accuracy isincreased with the decreased capacitance of the wiring capacitor, as wasdescribed before; however, it is impossible to decrease the capacitancebecause of the following reason: In order to allow an optical current toflow in the photo-diode PD, the reverse bias voltage VB across thephoto-diode PD must be sufficiently high. If the wiring capacitor CL issmall in capacitance, then the reverse bias voltage VB is decreased asthe voltage across the wiring capacitor CL increases. If the effectivereverse bias voltage VB of the photo-diode PD decreases in this manner,then it becomes impossible to supply the optical current. However, itshould be noted that the voltage across the wiring capacitor can beincreased as the capacitance of the wiring capacitor decreases as longas the reverse bias voltage VB does not adversely affect the opticalcurrent.

In the image reading device of matrix drive type described withreference to FIG. 8, the charges are transferred through the switchingelements T_(kn) to the wiring capacitors C_(L) and stored therein.Hence, in order to improve the charge transferring efficiency, it isnecessary to make C_(L) much larger than (C_(P) +C_(GD)). For thispurpose, it is necessary to reduce the voltage developed across thewiring capacitor C_(L) to a small fraction of that provided on the sideof the photo-electric conversion element 70. Hence, the voltage isamplified in the driving IC 81, thus increasing the sensitivity. In thisoperation, offset noises or random noises occur with the driving IC 81,thus lowering the S/N ratio.

SUMMARY OF THE INVENTION

Accordingly, an object of this invention is to eliminate theabove-described difficulties accompanying a conventional image readingdevice.

More specifically, an object of the invention is to provide a chargedetecting method in which a voltage detecting capacitor is made variablein capacitance, to increase an effective detection voltage thereby toimprove the signal detection accuracy, and a charge detecting circuitfor practicing the method.

A charge detecting method according to the invention comprises the stepsof setting a variable capacitor to a predetermined capacitance,injecting a charge into the variable capacitor, changing only thecapacitance of the variable capacitor with the charge maintained in thevariable capacitor, and detecting a voltage developed across thevariable capacitor.

Further, a charge detecting circuit according to the invention comprisesa variable capacitor whose capacitance is changed by external means,injecting means for injecting a charge into the variable capacitor, anddetecting means for detecting a voltage developed across the variablecapacitor.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIG. 1 is an equivalent circuit diagram, partly as a block diagram,showing an example of an image reading device which constitutes a firstembodiment of the invention;

FIG. 2 is an explanatory diagram for a description of the structure of avariable capacitor shown in FIG. 1;

FIG. 3 is an equivalent circuit diagram showing one bit in the imagereading device shown in FIG. 1;

FIG. 4 is a timing chart showing signals for the one bit in the imagereading device shown in FIGS. 1 and 3;

FIG. 5 is an equivalent circuit diagram showing one bit in anotherexample of the image reading device which constitutes a secondembodiment of the invention;

FIG. 6 is a timing chart showing signals for the one bit in the imagereading device shown in FIG. 5; and

FIGS. 7 and 8 are equivalent circuit diagrams showing examples of aconventional image reading device.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of this invention will be described with referenceto the accompanying drawings.

First, a matrix drive type image reading device which constitutes afirst embodiment of the invention, will be described with reference toFIG. 1.

As shown in FIG. 1, a photo-electric conversion element array is made upof a plurality of photo-electric conversion elements 70 corresponding tobits, and the photo-electric conversion elements 70 are connectedthrough switches Sll-Sln to variable capacitors CEXT. In FIG. 1, partscorresponding functionally to those which have been described withreference to FIG. 8 are accordingly designated by the same referencenumerals or characters.

The switches Sll-Sln are made up of thin film transistors, and thevariable capacitors CEXT are of a lamination structure. The switches andthe variable capacitors are formed in the same manufacturing process asthe photo-electric conversion elements 70 and the switching elementsT_(kn).

Each of the variable capacitors CEXT is so designed as to change itscapacitance into two values in response to external signals. Thestructure of each variable capacitor CEXT will be described withreference to FIG. 2. As shown in FIG. 2, the variable capacitor isformed by laying a metal electrode 21, an insulating layer 22, asemiconductor layer 23, and a metal electrode 24 one on another in thestated order. A pulse voltage is applied to the metal electrode 21.Examples of the material of the metal electrodes 21 and 24 are metalssuch as Au, Cr, Mo, Ti and Ta which are low in resistance and which arestable with temperature and chemicals so that they are not deterioratedduring photolithographing in the formation of the capacitor; or Oxideconductors such as SnO₂ and ITO. The insulation layer 22 is made of anoxide or nitride such as SiN_(x), SiO_(x), TaO_(x) and TaON_(x). Thesemiconductor layer 23 is made of p-type or n-type semiconductor whichis formed by doping impurities into amorphous silicon, or amorphoussilicon semiconductor including germanium or carbide.

When a voltage higher than that at the metal electrode 24 (for instance+5 V) is applied to the metal electrode 21, an electron storage layer isformed in the interface of the insulating layer 22 and the semiconductorlayer 23, as a result of which, in the variable capacitor, the regionfrom the metal electrode 24 up to the interface becomes low inresistance. Therefore, the capacitance between the metal electrodes 21and 24 may be represented by C1 corresponding to the thickness of theinsulating layer 22. When, on the other hand, a voltage lower than thatat the metal electrode 24 (for instance -5 V) is applied to the metalelectrode 21, the depletion of electron occurs on the semiconductor sideof the interface of the insulating layer 22 and the semiconductor layer23, thus providing high resistance. When the depletion has advancedsufficiently, the capacitance between the metal electrodes 21 and 24becomes C2 corresponding to the serial connection of the insulatinglayer 22 and the semiconductor layer 23. The capacitance C2 is smallerthan the capacitance C1. Therefore, the capacitance of the variablecapacitor CEXT can be changed with the potential of the metal electrode21.

Each of the switches Sll to Sln is so provided that, when each variablecapacitor CEXT is decreased in capacitance, the charge transferred tothe CEXT may not be redistributed to the overlap capacitors C_(GS)formed between the gates and sources of the respective switchingelements (T_(kn)). That is, it is used to electrically disconnect thevariable capacitor CEXT from the switching elements (T_(kn)), thereby toallow the variable capacitor to change in capacitance with the chargemaintained therein.

FIG. 3 shows the arrangement of a detecting circuit with the variablecapacitor CEXT in detail.

The detecting circuit comprises: the variable capacitor CEXT; a voltagecircuit 31 connected to the metal electrode 21 of the variable capacitorCEXT, to control the potential of the metal electrode 21; a reset switchRS connected between the metal electrodes 21 and 24, to reset thevariable capacitor CEXT; i.e., to discharge the latter; anequimagnification amplifier DA1 one input terminal of which is connectedto the metal electrode 24 of the variable capacitor CEXT; a differentialamplifier DA2 for amplifying the potential difference between the outputterminal of the amplifier DA1 and the metal electrode 21 of the variablecapacitor CEXT; and the above-described switch S1. The charge stored inthe variable capacitor CEXT changes the voltage across it in accordancewith the capacitance of the capacitor CEXT. In order to eliminate thechange in potential of the metal electrode 21, the voltage across thecapacitor CEXT is detected through the differential amplifier DA2.

The operation of the detecting circuit shown in FIGS. 1 and 3 will bedescribed with reference to FIG. 4, which is a timing chartcorresponding to one bit for a photo-electric conversion element.

In response to a gate pulse (Gk) and a switching pulse (PSln) for theswitch (Sln), the switching element (T_(kn)) and the switch (Sln) areturned on so that the photo-electric conversion element 70 is connectedto the variable capacitor CEXT. The switching pulse (PSln) is madelarger in pulse width than the gate pulse (Gk) so that the switch (Sln)is closed when the switching element (T_(kn)) is closed.

When the switching element (T_(kn)) is turned on by the gate pulse (Gk),the charge is transferred into the variable capacitor CEXT thecapacitance of which has been increased to C1.

Thereafter, the switch (Sln) is opened so that the photo-electricconversion element 70 is electrically disconnected from the variablecapacitor CEXT. Under this condition, a capacitance changing pulse isapplied to the metal electrode 21 of the variable capacitor CEXT tochange the capacitance of the latter into C2 (C2<C1). The variablecapacitor CEXT has been electrically disconnected from the switchingelement (T_(kn)) as was described above. Therefore, the charge will notbe distributed to the overlap capacitor C_(GS) of the switching element(T_(kn)), and accordingly, the variable capacitor CEXT can be changed incapacitance and in voltage with the charge maintained unchanged. Thechanged voltage (V_(CEXT)) across the variable capacitor CEXT isdetected by the differential amplifier DA2. Therefore, the variablecapacitor CEXT are discharged by the input reset signal (Rs).

FIG. 5 is an equivalent circuit showing one bit in a matrix drive typeimage reading device, which constitutes a second embodiment of theinvention. In FIG. 5, parts corresponding functionally to those whichhave been described with reference to FIG. 8 are therefore designated bythe same reference numerals or characters.

In the image reading device, for each bit including a photo-electricconversion element 70, a variable capacitor CEXT is provided which ismade up of a number (n) of capacitors CL_(l) -CL_(n). The terminals ofthe capacitors CL_(l) -CL_(n) are connected through a plurality ofswitches S2_(l) -S2_(n) as shown in FIG. 5 so that the capacitors can beconnected in parallel to one another through the switches. Furthermore,the terminals of the capacitors CL_(l) -CL_(n) are connected through aplurality of switches S3_(l) -S3_(n) as shown in FIG. 5, so that thecapacitors are connected in series to one another. That is, thecapacitors CL_(l) -CL_(n) are connected in parallel to one another byclosing the switches S2_(l) -S2_(n), and are connected in series to oneanother by closing the switches S3_(l) -S3_(n). More specifically, thecapacitance of the variable capacitor CEXT comprising the capacitorsCL_(l) -CL_(n) can be changed into two values by operating thoseswitches. A switching element T provided for the photo-electricconversion element 70 is connected to the end capacitor CL_(l), so that,when the parallel connection is switched over to the series connection,the potential at the terminal P is prevented from being changed; thatis, the transfer of charge to the switching element is prevented.

The variable capacitors CEXT are contained in the IC chip; however, theinvention is not limited thereto or thereby.

The operation of the detecting circuit shown in FIG. 5 will be describedwith reference to FIG. 6, which is a timing chart corresponding to onebit for the photo-electric conversion element 70.

In response to an S2 control pulse, the switches S2_(l) -S2_(n) areclosed so that the capacitors CL_(l) -CL_(n) forming the variablecapacitor CEXT are connected in parallel to one another. Assuming thatall the capacitors have a capacitance C, the resultant capacitance ofthe capacitor CEXT is (n×C).

When the switching element T is closed in response to a gate pulse, thecharge is transferred from the photo-electric conversion element 70 tothe variable capacitor CEXT whose capacitance is (n×C), to saturate thecapacitor.

When the switches S3_(l) -S3_(n) are closed by an S3 control pulse, thecapacitors CL_(l) -CL_(n) forming the variable capacitor CEXT areconnected in series to one another, so that the capacitance of thevariable capacitor CEXT is set to (C/n). In this case, the charges areredistributed in the capacitors CL_(l) -CL_(n) ; however, since theswitching element T is connected to the end capacitor CL_(l), thevoltage across the capacitor CL is maintained unchanged, and accordinglythe charge is not returned to the switching element T. Hence, in thesecond embodiment, unlike the first embodiment shown in FIG. 1, it isunnecessary to provide the switches (Sll-Sln in FIG. 1) for electricallydisconnecting the switching elements T from the variable capacitorsCEXT.

That is, in the second embodiment, the capacitance of the variablecapacitor CEXT can be changed with the charge maintained therein. Whenthe capacitance of the variable capacitor CEXT is changed in thismanner, the voltage applied to the amplifier A is changed, and thevoltage thus changed is detected as a detection signal.

The residual charge in the variable capacitor CEXT is removed byapplication of the input reset signal.

In the second embodiment, the switches S2_(l) -S2_(n) and S3₁ -S3_(n)and the variable capacitors CEXT including a number of capacitors CL_(l)-CL_(n) are formed in an IC chip, which is used to form the imagereading device. Therefore, the image reading device is simple in thefilm manufacturing process, and is high in manufacture yield.

As apparent from the foregoing description, according to the invention,a variable capacitor is charged with the capacitance set to a largevalue, and the voltage developed across the variable capacitor isdetected with the capacitance set to a small value. Hence, when thesignal detection is not carried out, the capacitance of the variablecapacitor is increased, so that the variable capacitor functions as alow impedance element which causes no voltage change; and when thesignal detection is carried out, the capacitance is decreased, so thatthe voltage to be detected is increased; that is, the S/N ratio isincreased, thus improving the sensitivity.

What is claimed is:
 1. A charge detecting circuit comprising:a variablecapacitor having a capacitance adapted to be changeable by externalmeans, wherein said variable capacitor comprises a plurality ofcapacitors, said plurality of capacitors being alternately connected toone another in series or in parallel to change said capacitance of saidvariable capacitor; injecting means for injecting a charge into saidvariable capacitor; and detecting means for detecting a voltagedeveloped across said variable capacitor.
 2. A charge detecting circuitas claimed in claim 1, wherein the capacitance of said variablecapacitor is changed by an external voltage.
 3. A charge detectingcircuit as claimed in claim 1, wherein said injecting means is connectedthrough a switching element to a charge generating source.
 4. A chargedetecting circuit as claimed in claim 1, wherein said detecting means isa differential amplifier.
 5. A charge detecting circuit as claimed inclaim 1, wherein said variable capacitor is formed by laying a firstconductor layer, an insulating layer, a semiconductor layer, and asecond conductor layer one on another in the stated order.
 6. A chargedetecting circuit as claimed in claim 1, wherein upon series connectionof said plurality of capacitors to one another, a first terminal of afirst one of said plurality of capacitors is connected to ground and asecond terminal of said first one of said plurality of capacitors isconnected to said injecting means.
 7. A charge detecting methodcomprising the steps of:setting a variable capacitor to a predeterminedcapacitance, said variable capacitor comprising a plurality ofindividual capacitors; establishing a charge on said variable capacitor;alternately connecting said plurality of individual capacitors in seriesor in parallel to change said predetermined capacitance of said variablecapacitor while maintaining said charge on the variable capacitor;detecting a voltage developed across the variable capacitor.
 8. An imagereading device, comprising:a plurality of photoelectric conversionelements arranged in an array, each photoelectric conversion elementproducing an optical charge in response to light reflected from animage; a plurality of variable capacitors, each one of said plurality ofvariable capacitors having a capacitance and storing the optical chargeof a respective photoelectric conversion element; means for changingsaid capacitance of each one of said plurality of variable capacitorswhile maintaining the stored optical charge; and means for detecting avoltage developed across each one of said plurality of variablecapacitors.
 9. The image reading device of claim 8, wherein the meansfor changing includes a plurality of switches, each of said switchesbeing interposed between a respective photoelectric conversion elementand a corresponding variable capacitor.
 10. The image reading device ofclaim 8, wherein the means for changing includes means for changing anexternal voltage applied to each of said variable capacitors.
 11. Theimage reading device of claim 8 ,wherein the means for detectingincludes a differential amplifier.